Study on Leakage Current Reduction Technique in VLSI Design

  • Rafeekun Nisha Chhattisgarh Swami Vivekanand Technical University, Newai
  • Prashant Dwivedi Chhattisgarh Swami Vivekanand Technical University, Newai
  • Monica Ramteke Chhattisgarh Swami Vivekanand Technical University, Newai
Keywords: VLSI, CMOS, GIDL, DIBL, Vgs, tox, FET, Mox, MTCMOS

Abstract

In the present scenario, designing a circuit with low power has become very important and challenging task, low power devices are the need of present electronics industries. In VLSI circuit design, power dissipation and leakage present are the critical design structures as they show anvital role in act of the battery. Power management of chip is the major challenge. Leakage power is a crucial parameter as the technology is shrinking (180 nanometer, 90 nanometer, 45 nanometer).The leakage current is increasing very fast so numerous technique has been proposed for leakage reduction in CMOS digital integrated circuit. This review paper demonstrates the various reduction showcase for CMOS integrated circuited.

References

[1]. Gautam, M., & Akashe, S. (2013, February). Transistor gating: reduction of leakage current and power in full subtractor circuit. In 2013 3rd IEEE International Advance Computing Conference (IACC) (pp. 1514-1518). IEEE.
[2]. Roy, K., & Prasad, S. C. (2009). Low-power CMOS VLSI circuit design. John Wiley & Sons.
[3].Yeap, G. K., & Najm, F. N. (Eds.). (1996). Low power VLSI design and technology (Vol. 6). World Scientific.
[4]. Roy, K., Mukhopadhyay, S., & Mahmoodi-Meimand, H. (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2), 305-327.
[5]. Singh, S., Kaur, B., Kaushik, B. K., & Dasgupta, S. (2012, December). Leakage current reduction using modified gate replacement technique for CMOS VLSI circuit. In 2012 International Conference on Communications, Devices and Intelligent Systems (CODIS) (pp. 464-467). IEEE.
[6]. Gupta, T. K., & Khare, K. (2013). A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits. International Journal of Computer Applications, 61(5).
[7]. Ning, T. H., & Taur, Y. (1998). Fundamentals of modern VLSI devices.
[8]. Deepaksubramanyan, B. S., & Nunez, A. (2007, August). Analysis of subthreshold leakage reduction in CMOS digital circuits. In 2007 50th Midwest Symposium on Circuits and Systems (pp. 1400-1404). IEEE.
[9]. Yang, S., Wolf, W., Vijaykrishnan, N., Xie, Y., & Wang, W. (2005, January). Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits. In 18th international conference on VLSI design held jointly with 4th international conference on embedded systems design (pp. 165-170). IEEE.
[10]. Lee, D., Kwong, W., Blaauw, D., & Sylvester, D. (2003, June). Analysis and minimization techniques for total leakage considering gate oxide leakage. In Proceedings of the 40th annual Design Automation Conference (pp. 175-180). ACM.
[11]. Kumari, K., Agarwal, A., & Agarwal, K. (2014). Review of leakage power reduction in CMOS circuits. American Journal of Electrical and Electronic Engineering, 2(4), 133-136.
[12]. Seomun, J., & Shin, Y. (2009). Design and optimization of power-gated circuits with autonomous data retention. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(2), 227-236.
[13]. Tonk, A., & Goyal, S. (2015). A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design. International Journal of Advanced Research in Computer and Communication Engineering, 3(2), 554-558.
[14]. Priya, M. G., Baskaran, K., & Krishnaveni, D. (2012). Leakage power reduction techniques in deep submicron technologies for VLSI applications. Procedia Engineering, 30, 1163-1170.
[15]. Hanchate, N., & Ranganathan, N. (2004). LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 196-205.
[16]. E. Upasani Dhananjay, Shrote B. Sandip, “Standby leakage reduction in nanoscale CMOS VLSI circuits,” International Journal on computer applications, vol. 7, September 2010
[17]. Kim, S. H., & Mooney III, V. J. (2006). The Sleepy Keeper Approach: Methodology, Layout and Power Results for a 4-bit Adder. Georgia Institute of Technology.
[18]. Wei, L., Chen, Z., Johnson, M., Roy, K., De, V., & De, V. (1998, May). Design and optimization of low voltage high performance dual threshold CMOS circuits. In Proceedings of the 35th annual Design Automation Conference (pp. 489-494). ACM.
[19]. Hanchate, N., & Ranganathan, N. (2004). LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 196-205.
[20]. Gu, R.X and Elmasry M.I, “Power dissipation analysis and optimization of deep sub-micron CMOS digital circuits,”IEEE Journal of solid-state circuits, vol. 31, pp. 707-713, 1996.
[21]. Shauly, E. N. (2012). CMOS leakage and power reduction in transistors and circuits: process and layout considerations. Journal of Low Power Electronics and Applications, 2(1), 1-29.
[22]. Chen, Z., Johnson, M., Wei, L., & Roy, W. (1998, August). Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks. In Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No. 98TH8379) (pp. 239-244). IEEE.
[23]. Lee, D., Blaauw, D., & Sylvester, D. (2004). Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 155-166.
[24]. MP, P. K., & Fletcher, A. A. A Survey on Leakage Power Reduction Techniques by Using Power Gating Methodology.
[25]. Dadoria, A. K., Khare, K., & Singh, R. P. (2015, September). A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits. In 2015 International Conference on Computer, Communication and Control (IC4) (pp. 1-6). IEEE.
[26]. Rahman, H., & Chakrabarti, C. (2004, May). A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512) (Vol. 2, pp. II-297). IEEE.
[27]. Abdollahi, A., Fallah, F., & Pedram, M. (2004). Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 140-154.
[28]. Saxena, N., & Soni, S. (2013). Leakage current reduction in CMOS circuits using stacking effect. International Journal of Application or Innovation in Engineering & Management, 2(11), 213-216.
Published
2019-07-29
Section
Articles